A static random access memory (SRAM) includes an array of individual bit cells. “Read-disturb” occurs when the SRAM is accessed for a read. Read-disturb can occur as a result of injecting charge into a bit cell's storage nodes from the bit cell's bit lines when the bit cell's word line is asserted. The injection of the charge generates noise at the storage nodes and destabilizes the bit cell. Read-disturb can have other causes such as RTS (random telegraph signals) and particle strikes. If the disturb noise exceeds the tolerance of the bit cell (the static noise margin (SNM)), then the value stored in the bit cell flips (e.g., changes from low to high, from binary logic zero to binary logic one, or vice versa), corrupting the data stored by the SRAM.
As memory technologies advance, the SNM of SRAM continues to decrease while the total number of bit cells in an integrated circuit (IC) design continues to increase. As a result, the probability of an SRAM failure related to read-disturb increases significantly. Thus, without an effective way to control or to reduce read-disturb in SRAMs, making an IC or a system-on-chip (SOC) product that includes SRAM may become impractical.
Various solutions have been proposed and implemented in an attempt to mitigate read-disturb. However, each of these solutions has its shortcomings. For example, they may utilize either multi-regulator or replica-access-transistor (RAT) schemes, which increase the complexity of the design, can make the design more sensitive to process, voltage, and temperature (PVT) variations, and can introduce a significant leakage current.
Another proposed solution uses a multiplexed supply voltage for the word line, to raise instead of lower the word line voltage. As a result, the complexity of the design is increased, performance is slowed, and reliability may be an issue due to the excessive stress put on the pass gate devices by the method of raising supply voltage.
Yet another proposed solution uses a delay mechanism. However, the delay circuitry slows performance and thus renders the scheme impractical for modern SRAM designs.